Network elements such as routers and switches utilize network processors to perform packet processing operations. These network processors are typically implemented in the form of integrated circuits, and include phase-locked loop (PLL) based clock generation circuitry which generates clock signals for the processor core as well as one or more additional clock domains. These additional clock domains may include, for example, domains associated with different types of internal or external memory, such as double data rate (DDR) memory, a host processor, other logic circuitry, etc. It is often desirable to operate the various processor clock domains at different clock rates. For example, the DDR memory domain may operate at a higher clock rate than the processor core. Also, power consumption can often be reduced in a network processor by operating certain domains at clock rates which vary depending upon processing conditions and other factors. Accordingly, the clock generation circuitry is preferably configurable to provide different clock signals to the different domains.
The configuration of the clock generation circuitry is typically achieved in conventional practice by providing the network processor integrated circuit with a number of external clock configuration pins. By applying appropriate logic signals to these external clock configuration pins, usually in conjunction with a circuit reset operation, one can control the configuration of the clock generation circuitry and the particular type of clock signals that it supplies to the various clock domains.
A significant problem associated with this conventional practice is that the number of external pins available on a typical network processor integrated circuit is usually very limited. Increasing the number of pins dedicated to clock configuration can have a negative impact on integrated circuit cost or board design. As a result, the number of different configurations that may be supported is unduly restricted, and the clock configuration does not have the desired level of flexibility. Alternative approaches, such as those involving the use of flash memory, can add excessive cost and complexity to the processor.
It is therefore apparent that a need exists for improved clock generation techniques for use in network processors and other types of processors, so as to provide greater flexibility in clock configuration while avoiding the need for additional pins or flash memory.